LCD控制器方面留學(xué)生essay寫作指導(dǎo)-LCD CONTROLLER
15-1
OVERVIEW
The LCD controller in the S3C2410X consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level grayscale) mode on a monochrome LCD, using a time-based dithering algorithm and Frame Rate Control (FRC)method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel(4096-level color) for interfacing with STN LCD.
It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palettized
TFT color LCD panel, and 16-bit per pixel and 24-bit per pixel for non-palettized true-color display.
The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate.
FEATURES
STN LCD displays:
— Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display type
— Supports the monochrome, 4 gray levels, and 16 gray levels
— Supports 256 colors and 4096 colors for color STN LCD panel
— Supports multiple screen size
Typical actual screen size: 640?480, 320?240, 160?160, and others
Maximum virtual screen size is 4Mbytes.
Maximum virtual screen size in 256 color mode: 4096?1024, 2048?2048, 1024?4096, and others
TFT LCD displays:
— Supports 1, 2, 4 or 8-bpp (bit per pixel) palettized color displays for TFT
— Supports 16-bpp non-palettized true-color displays for color TFT
— Supports 24-bpp non-palettized true-color displays for color TFT
— Supports maximum 16M color TFT at 24bit per pixel mode
— Supports multiple screen size
Typical actual screen size: 640?480, 320?240, 160?160, and others
Maximum virtual screen size is 4Mbytes.
Maximum virtual screen size in 64K color mode: 2048?1024 and others
15-2
COMMON FEATURES
The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include:
— Dedicated interrupt functions (INT_FrSyn and INT_FiCnt)
— The system memory is used as the display memory.
— Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling)
— Programmable timing control for different display panels
— Supports little and big-endian byte ordering, as well as WinCE data formats#p#分頁標題#e#
— Supports SEC TFT LCD panel (SAMSUNG 3.5??Portrait/256K Color/Reflective a-Si TFT LCD)
LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit
LTS350Q1-PD2: TFT LCD panel only
NOTE
WinCE doesn't support the 12-bit packed data format.
Please check if WinCE can support the 12-bit color-mode.
EXTERNAL INTERFACE SIGNAL
VFRAME/VSYNC/STV : Frame synchronous signal (STN)/vertical synchronous signal (TFT)/SEC TFT signal
VLINE/HSYNC/CPV : Line synchronous pulse signal (STN)/horizontal sync signal (TFT)/SEC TFT signal
VCLK/LCD_HCLK : Pixel clock signal (STN/TFT)/SEC TFT signal
VD[23:0] : LCD pixel data output ports (STN/TFT/SEC TFT)
VM/VDEN/TP : AC bias signal for the LCD driver (STN)/data enable signal (TFT)/SEC TFT signal
LEND/STH : Line end signal (TFT)/SEC TFT signal
LCD_PWREN : LCD panel power enable control signal
LCDVF0 : SEC TFT Signal OE
LCDVF1 : SEC TFT Signal REV
LCDVF2 : SEC TFT Signal REVB
The 33 output ports in total includes 24 data bits and 9 control bits
15-3
BLOCK DIAGRAM
The S3C2410X LCD controller is used to transfer the video data and to generate the necessary control signals ,such as VFRAME, VLINE, VCLK, VM, and so on. In addition to the control signals, the S3C2410X has the data ports for video data, which are VD[23:0] as shown in Figure 15-1. The LCD controller consists of a REGBANK,LCDCDMA, VIDPRCS, TIMEGEN, and LPC3600 (See the Figure 15-1 LCD Controller Block Diagram). The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which can transfer the video data in frame memory to LCD driver automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD[23:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on.
Figure 15-1. LCD Controller Block Diagram
The description of data flow is as follows:
FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode (consecutive memory fetching of 4 words (16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When the transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 28 words, which consists of 12 words FIFOL and 16 words FIFOH, respectively. The S3C2410X has two FIFOs to support the dual scan display mode. In case of single scan mode, one of the FIFOs (FIFOH) can only be used.#p#分頁標題#e#
15-4
LCD CONTROLLER SPECIAL REGISTERS
LCD Control 1 Register
Register Address R/W Description Reset Value
LCDCON1 0X4D000000 R/W LCD control 1 register 0x00000000
LCDCON1 Bit Description Initial State
LINECNT
(read only) [27:18] Provide the status of the line counter.
Down count from LINEVAL to 0 0000000000
CLKVAL [17:8] Determine the rates of VCLK and CLKVAL[9:0].
STN: VCLK = HCLK / (CLKVAL * 2)
TFT: VCLK = HCLK / [(CLKVAL+1) * 2] 0000000000
MMODE [7] Determine the toggle rate of the VM.
0 = Each Frame,
1 = The rate defined by the MVAL 0
PNRMODE [6:5] Select the display mode.
00 = 4-bit dual scan display mode (STN)
01 = 4-bit single scan display mode (STN)
10 = 8-bit single scan display mode (STN)
11 = TFT LCD panel 00
BPPMODE [4:1] Select the BPP (Bits Per Pixel) mode.
0000 = 1 bpp for STN, Monochrome mode
0001 = 2 bpp for STN, 4-level gray mode
0010 = 4 bpp for STN, 16-level gray mode
0011 = 8 bpp for STN, color mode
0100 = 12 bpp for STN, color mode
1000 = 1 bpp for TFT
1001 = 2 bpp for TFT
1010 = 4 bpp for TFT#p#分頁標題#e#
1011 = 8 bpp for TFT
1100 = 16 bpp for TFT
1101 = 24 bpp for TFT 0000
ENVID [0] LCD video output and the logic enable/disable.
0 = Disable the video output and the LCD control signal.
1 = Enable the video output and the LCD control signal. 0
LCD Control 2 Register
Register Address R/W Description ReReset Value
LCDCON2 0X4D000004 R/W LCD control 2 register 0x00000000
LCDCON2 Bit Description Initial State
VBPD [31:24] TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period.
STN: These bits should be set to zero on STN LCD. 0x00
LINEVAL [23:14] TFT/STN: These bits determine the vertical size of LCD panel. 0000000000
VFPD [13:6] TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period.
STN: These bits should be set to zero on STN LCD. 00000000
VSPW [5:0] TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines.
STN: These bits should be set to zero on STN LCD. 000000
LCD Control 3 Register#p#分頁標題#e#
Register Address R/W Description Reset Value
LCDCON3 0X4D000008 R/W LCD control 3 register 0x00000000
LCDCON3 Bit Description Initial state
HBPD (TFT) [25:19] TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. 0000000
WDLY (STN) STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved.
00 = 16 HCLK, 01 = 32 HCLK,
10 = 48 HCLK, 11 = 64 HCLK
HOZVAL [18:8] TFT/STN: These bits determine the horizontal size of LCD panel.HOZVAL has to be determined to meet the condition that total bytes of 1 line are 4n bytes. If the x size of LCD is 120 dot in mono mode, x=120 cannot be supported because 1 line consists of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line is composed of 16 bytes (2n). LCD panel driver will discard the additional 8 dot. 00000000000
HFPD (TFT) [7:0] TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. 0X00
LINEBLANK
(STN) STN: These bits indicate the blank time in one horizontal line duration time. These bits adjust the rate of the VLINE finely. The unit of LINEBLANK is HCLK X 8.
Ex) If the value of LINEBLANK is 10, the blank time is inserted to VCLK during 80 HCLK.
LCD Control 4 Register
#p#分頁標題#e#
Register Address R/W Description Reset Value
LCDCON4 0X4D00000C R/W LCD control 4 register 0x00000000
LCDCON4 Bit Description Initial state
MVAL [15:8] STN: These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. 0X00
HSPW(TFT) [7:0] TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. 0X00
WLH(STN) STN: WLH[1:0] bits determine the VLINE pulse's high level width by counting the number of the HCLK.
WLH[7:2] are reserved.
00 = 16 HCLK, 01 = 32 HCLK,
10 = 48 HCLK, 11 = 64 HCLK
LCD Control 5 Register
Register Address R/W Description Reset Value
LCDCON5 0X4D000010 R/W LCD control 5 register 0x00000000
LCDCON5 Bit Description Initial state
Reserved #p#分頁標題#e#[31:17] This bit is reserved and the value should be '0'. 0
VSTATUS [16:15] TFT: Vertical Status (read only).
00 = VSYNC 01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch 00
HSTATUS [14:13] TFT: Horizontal Status (read only).
00 = HSYNC 01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch 00
BPP24BL [12] TFT: This bit determines the order of 24 bpp video memory.
0 = LSB valid 1 = MSB Valid 0
FRM565 [11] TFT: This bit selects the format of 16 bpp output video data.
0 = 5:5:5:1 Format
1 = 5:6:5 Format 0
INVVCLK [10] STN/TFT: This bit controls the polarity of the VCLK active edge.
0 = The video data is fetched at VCLK falling edge
1 = The video data is fetched at VCLK rising edge 0
INVVLINE [9] STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity.
0 = Normal 1 = Inverted 0
INVVFRAME [8] STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity.
0 = Normal 1 = Inverted 0
INVVD [7] STN/TFT: This bit indicates the VD (video data) pulse polarity.
0 = Normal 1 = VD is inverted. 0
INVVDEN [6] TFT: This bit indicates the VDEN signal polarity.#p#分頁標題#e#
0 = Normal 1 = Inverted 0
INVPWREN [5] STN/TFT: This bit indicates the PWREN signal polarity.
0 = Normal 1 = Inverted 0
INVLEND [4] TFT: This bit indicates the LEND signal polarity.
0 = Normal 1 = Inverted 0
PWREN [3] STN/TFT: LCD_PWREN output signal enable/disable.
0 = Disable PWREN signal
1 = Enable PWREN signal 0
ENLEND [2] TFT: LEND output signal enable/disable.
0 = Disable LEND signal
1 = Enable LEND signal 0
BSWP [1] STN/TFT: Byte swap control bit.
0 = Swap Disable
1 = Swap Enable 0
HWSWP [0] STN/TFT: Half-Word swap control bit.
0 = Swap Disable
1 = Swap Enable 0
附錄二(翻譯)
15 LCD控制器
15-1
概述
S3C2410X中的LCD控制器主要用來實現(xiàn)從位于內(nèi)存中的視頻緩沖到外部LCD驅(qū)動的邏輯轉(zhuǎn)換。
該LCD控制器支持單色,2位每像素(4級灰度)或者4位每像素(16級灰度)模式的一個單色液晶顯示器,使用基于時間的都得算法和幀速率控制(RFC)方法并且它可以和帶有彩色液晶面板的8位每像素(256級彩色)和12位每像素(4096級彩色)接口的液晶顯示器連接。
它可以支持1位每像素,2位每像素,4位每像素,和8位每像素的TFT彩色液晶面板,和16位每像素以及24位每像素的非調(diào)色板的真彩色顯示。
該LCD控制器可以編程,以滿足不同橫向、縱向比,不同數(shù)據(jù)線寬度的接口,接口時序和刷新頻率的顯示器的需求。
特征:
LCD液晶顯示器:
——支持三種類型的液晶面板:4位雙掃面,4位單掃描,和8位單掃描顯示類型#p#分頁標題#e#
——支持單色,4灰階層次,16灰階層次
——支持256色和4096色的CSTN彩色液晶面板
——支持多種屏幕尺寸
典型的實際屏幕尺寸:640*480,320*240,160*160和其他最大虛擬屏幕尺寸4Mbytes,256色模式大虛擬屏幕尺寸:4096*1024,2048*2048,1024*4096,以及其他。
TFT液晶顯示器:
——支持1、2、4或者8位每像素的調(diào)色板彩色TFT顯示器
——支持16位每像素非調(diào)色板真彩色TFT顯示器
——支持24位每像素非調(diào)色板真彩色TFT顯示器
——支持最大16M彩色TFT在24位每像素模式下
——支持多種屏幕尺寸
典型的實際屏幕尺寸:640*480,320*240,160*160,和其他最大虛擬屏幕是4Mbytes,在64K色模式下最大虛擬屏幕是2048*1024和其它。
15-2
共同特點
該LCD控制器擁有專用的DMA用來從位于系統(tǒng)內(nèi)存中的視頻緩沖區(qū)獲取圖像數(shù)據(jù),它的功能還包括:
——專用中斷功能(TNT_FrSyn 和 INT_FiCnt)
——系統(tǒng)內(nèi)存作為顯示內(nèi)存
——支持多個虛擬現(xiàn)實屏幕(支持硬件水平/垂直滾動)
——可編程定時控制不同的顯示面板
——支持小和大端字節(jié)序,以及嵌入式數(shù)據(jù)格式
——支持SEC TFT液晶面板(三星3.5英寸/256K色/反射的 TFT 液晶顯示器)
LTS350Q1-PD1:TFT液晶面板的觸摸屏和前燈組
LTS350Q1-PD2:TFT液晶面板
注意:
嵌入式不支持12位便攜數(shù)據(jù)格式,請檢查嵌入式是否支持12位彩色顯示模式。
外部接口信號:
VFRAME/VSYNC/STV :幀同步信號(LCD)/垂直同步信號(TFT)/第二TFT信號
VLINE/HSYNC/CPV:行同步信號(STN)/水平同步信號(TFT)/第二TFT信號
VCLK/LCD_HCLK::像素時鐘信號(STN/TFT)/第二TFT信號
VD[23:0]:LCD像素輸出端口(STN/TFT/SEC TFT)
VM/VDEN/TP:交流偏置信號的LCD驅(qū)動(STN)/數(shù)據(jù)使能信號(TFT)/第二TFT信號
LEND/STH:結(jié)束信號(TFT)/第二TFT信號
LCD_PWREN:LCD電源控制信號
LCDVF0:第二TFT光電信號
LCDVF1:第二TFT翻轉(zhuǎn)信號
LCDVF2:第二TFTR EVB信號
33位輸出端口包括24位數(shù)據(jù)端口和9位控制端口
15-3
框圖
圖 15-1 LCD 控制器框圖
S3C2410X的LCD控制器是用來傳輸視頻數(shù)據(jù)和產(chǎn)生必要的控制信號,例如VFRAME、VLINE、VCLK、VM等等。除了這些控制信號,S3C2410X有數(shù)據(jù)端口傳輸視頻數(shù)據(jù),VD[23:0]如圖15-1所示。在該LCD控制器由寄存器組(REGBANK)、DMA通道(LCDCDMA)、時序信號發(fā)生器(TIMEGEN)、時序控制單元(LPC3600)、視頻信號處理(VIDPRCS)。在寄存器組中有17個可編程寄存器和256*16的調(diào)色板存儲器來配置LCD控制器。DMA通道是一個專用DMA,它可以自動將視頻數(shù)據(jù)幀存儲器中等的視頻數(shù)據(jù)到LCD驅(qū)動器。通過使用這個特殊的MDA,視頻數(shù)據(jù)可以顯示在屏幕上無需CPU干預(yù)。視頻信號處理器從DMA通道接收視頻數(shù)據(jù),改變成一個適合的數(shù)據(jù)格式,例如4/8位單掃描或者4位雙掃描模式,之后通過VD[23:0]數(shù)據(jù)接口傳輸?shù)絃CD驅(qū)動器。時序信號發(fā)生器包含可編程邏輯支持對于接口時序、刷新頻率的不同LCD驅(qū)動器的要求。該模塊生成VFRAME,VLINE,VCLK,VM等。數(shù)據(jù)流的描述如下:DMA通道包含F(xiàn)IFO的內(nèi)存模塊。當FIFO模塊中的數(shù)據(jù)空或者部分空時,DMA通道請求數(shù)據(jù)并從幀內(nèi)存存儲器基于突發(fā)內(nèi)存?zhèn)鬏斈J剑看瓮话l(fā)請求連續(xù)取4字(16位),在總線傳輸時不允許轉(zhuǎn)讓總線使用權(quán))當轉(zhuǎn)讓的請求被內(nèi)存控制器中的總線仲裁機構(gòu)接受,將有四個字的連續(xù)數(shù)據(jù)從系統(tǒng)內(nèi)存?zhèn)鬏數(shù)紽IFO模塊。FIFO模塊的大小為28個字,分別是12個字的FIFIOL和16個字的FIFOH。S3C2410X中有2個FIFO模塊去支持雙掃描顯示模塊。如果在單掃描顯示模式,只能使用其中的一個FIFO模塊(FIFOH)。#p#分頁標題#e#
15-4
LCD控制器特殊寄存器
LCD控制器 寄存器1
寄存器 地址 讀/寫 描述 復(fù)位值
LCDCON1 0x4D000000 讀/寫 LCD控制器寄存器1 0x00000000
LCDCON1 位 描述 初始狀態(tài)
LINECNT
(只讀) [27:18] 提供計數(shù)狀態(tài)
從LINEVAL減到0 0000000000
CLKVAL [17:8] 決定VCLK和CLKVAL[9:0]的值
STN:VCLK=HCLK/(CLKVAL*2)
TFT:VCLK=HCLK/[(CLKVAL+1)*2] 0000000000
MMODE [7] 決定VM的切換平率
0=每幀
1=由MVAL確定的值 0
PNRMODE [6:5] Select the display mode
00=4位雙掃描模式
01=4位單掃描模式
10=8位單掃描模式
11=TFT 液晶面板 00
BPPMDOE [4:1] 選擇每像素位模式
0000=1位每像素(STN),黑白模式
0001=2位每像素(STN),4級灰度
0010=4位每像素(STN),16級灰度
0011=8位每像素(STN),彩色模式
0100=12位每像素(STN),彩色模式
1000=1位每像素(TFT)
1001=2位每像素(TFT)
1010=4位每像素(TFT)
1011=8位每像素(TFT)
1100=16位每像素(TFT)
1101=24位每像素(TFT) 0000
ENVID #p#分頁標題#e#[0] LCD視頻輸出的啟用/禁用
0=不允許視頻輸出和LCD控制信號
1=允許視頻輸出和LCD控制信號 0
LCD控制器寄存器2
寄存器 地址 讀/寫 描述 復(fù)位值
LCDCON2 0x4D000004 讀/寫 LCD控制寄存器2 0x00000000
LCDCON2 Bit 描述 Initial State
VBPD [31:24] TFT:在垂直同步以后,垂直后門廊是在一幀的開始時的無效行數(shù)
STN:設(shè)置為0 0x00
LINEVAL [23:14] 這些位確定液晶面板的垂直尺寸 0000000000
VFPD [13:6] TFT:在垂直同步以前,垂直前門廊是在一幀的結(jié)束時的無效行數(shù)
STN:設(shè)置為0 00000000
VSPW [5:0] TFT:垂直同步脈沖寬度確定VSYNC脈沖的高水平寬度通過計數(shù)無效行的數(shù)目。
STN:設(shè)置為0 000000
LCD 控制器寄存器3
寄存器 地址 讀/寫 描述 復(fù)位值
LCDCON3 0x4D000008 讀/寫 LCD控制寄存器3 #p#分頁標題#e#0x00000000
LCDCON3 位 描述 初始值
HBPD(TFT) [25:19] TFT: 臥式后門廊是一些VCLK時期在下降沿的HSYNC和有效數(shù)據(jù)開始之間 0000000
WDLY(STN) STN:WDLY[1:0]位決定VLINE和VCLK之間的延遲通過計數(shù)HCLK。WDLY[7:2]保留。
00=16HCLK,01=32HCLK,10=48HCLK,11=64HCLK
HOZVAL [18:8] TFT/STN:這些位數(shù)決定液晶面板的橫向尺寸,HOZVAL被確定滿足1行的總字節(jié)數(shù)是4的倍數(shù)。如果LCD的X尺寸是120在單色模式下,x=120將不被支持因為1行包含15個字節(jié),x=128在單色模式下將被支持,因為一行包含16個字節(jié)(2的倍數(shù))。液晶面板驅(qū)動器將拋棄額外的8點 00000000000
HFPD(TFT) [7:0] TFT: 臥式前門廊是一些VCLK時期在上升沿的HSYNC和有效數(shù)據(jù)結(jié)束之間 0x00
LINEBLANK STN:這些位表明空白時間顯示在一個水平線持續(xù)時間。這些位精確的調(diào)整VLINE的值。LINEBLANK的單位是HCLK*8.(如果LINEBLANK的值是10,空白時間在80HCLK被插入到VCLK)
LCD控制器 寄存器4
寄存器 地址 讀/寫 描述 復(fù)位值
LCDCON4 0x4D00000C 讀/寫 LCD控制寄存器4 0x00000000
LCDCON4 位 描述 初始值
MVAL #p#分頁標題#e#[15:8] STN:這些位定義VM信號的切換值,如果MMODE位被設(shè)置為‘1’ 0X00
HSPW(TFT) [7:0] TFT: 水平同步脈沖寬度確定HSYNC脈沖的高度寬度通過計數(shù)VCLK 數(shù)目。 0X00
WLH(STN) STN:WLH[1:0]位決定VLINE脈沖的高度寬度通過計數(shù)HCLK的數(shù)目。
WLH[7:2]保留
00 = 16 HCLK, 01 = 32 HCLK,
10 = 48 HCLK, 11 = 64 HCLK
LCD控制器 寄存器5
寄存器 地址 讀/寫 描述 復(fù)位值
LCDCON5 0x4D000010 讀/寫 LCD控制寄存器5 0x00000000
LCDCON5 位 描述 初始值
保留 [31:17] 這些位保留且值為0 0
VSTATUS [16:15] TFT:垂直狀態(tài)(只讀)
00=VSYNC 01=BACK Porch
10=ACTIVE 11=FRONT Porch 00
HSTATUS [14:13] TFT:水平狀態(tài)(只讀)
00=VSYNC 01=BACK Porch
10=ACTIVE 11=FRONT Porch 00
BPP24BL [12] TFT:這位決定了24位每像素視頻內(nèi)存的格式
0=最低為有效 1=最高為有效 0
FRM565 [11] TFT:這位選擇16位每像素輸出視頻數(shù)據(jù)的順序
0=5:5:5:1格式 1=5:6:5格式 0
INVVCLK [10] STN/TFT:這位控制VCLK的有效邊緣
0=視頻數(shù)據(jù)獲取在VCLK下降沿
1=視頻數(shù)據(jù)獲取在VCLK上升沿 0
INVVLINE [9] STN/TFT:這為表明VLINE/HSYNC
的脈沖極性
0=正常
1=顛倒 0
INVVFRAME [8] STN/TFT:這位表明VFRAME/VSYNC的脈沖極性
0=正常
1=顛倒 0
INVVD [7] STN/TFT:這位表明視頻數(shù)據(jù)的脈沖極性
0=正常
1=視頻數(shù)據(jù)顛倒 0
INVVDEN [6] TFT:這位表明VDEN信號極性
0=正常
1=顛倒 0
INVPWREN [5] TFT:這位表明PWREN信號極性
0=正常
1=顛倒 0
INVLEND [4] TFT:這位表明LEND信號極性
0=正常
1=顛倒 0
PWREN [3] STN/TFT:這位表明LCD_POWREN輸出信號信啟用/禁用
0=啟用
1=禁用 0
ENLEND [2] STN/TFT:這位表明LEND輸出信號信啟用/禁用
0=啟用
1=禁用 0
BSWP [1] STN/TFT:字節(jié)交換控制位
0=交換啟用
1=交換禁用 0
HWSWP [0] STN/TFT:半字交換控制位
0=交換啟用
1=交換禁用 0